Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily-doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). The source/drain regions 105 may, for example, be lightly-doped drain (LDD) source/drain regions as shown. As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as SiO.sub.2. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
In a completed device structure, the source/drain regions 105 and gate electrode 103 are typically contacted by metal lines in order to interconnect these structures with other elements of the device. To facilitate contact between a metal line and the source/drain regions 105 or the gate electrode 103, a silicidation layer 111 is typically formed over the source/drain regions 105 and the gate electrode 103 prior to forming the metal line. The silicidation layer 111 is typically formed by depositing a layer of metal, such as tungsten or cobalt, over the substrate 101 and annealing the wafer. During the annealing process, the deposited metal reacts with underlying silicon and forms a metal silicidation layer. The thickness of the silicidation layer 111 is limited by the depth of the source/drain junction as the silicidation layer 111 must be spaced from the source/drain junction to maintain source/drain integrity. Typical thicknesses of the silicidation layer are less than 3/4 of the depth of the source/drain junction. A more detailed description of silicidation layers and the fabrication thereof may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 143-153 and 157-158.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region 107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
The depth of the source/drain region is an important dimension which is scaled down as the device structure is made smaller. Using the conventional process described above, as the source/drain junction depth is reduced, the thickness of the silicidation layer must be reduced in order to maintain spacing between the source/drain junction and the silicidation layer and avoiding shorting the source/drain region. Reducing the thickness of the silicidation layer however increases the sheet resistance of the layer and negatively impacts the performance of the device. Consequently, using conventional processes there is a trade-off between the depth of the source/drain region and the depth of the silicidation layer. This trade-off limits further scaling of semiconductor devices.